pynq.lib.dma Module

class pynq.lib.dma.DMA(description, *args, **kwargs)

Bases: pynq.overlay.DefaultIP

Class for Interacting with the AXI Simple DMA Engine

This class provides two attributes for the read and write channels. The read channel copies data from the stream into memory and the write channel copies data from memory to the output stream. Both channels have an identical API consisting of transfer and wait functions. If interrupts have been enabled and connected for the DMA engine then wait_async is also present.

Buffers to be transferred must be a PynqBuffer object allocated through pynq.allocate() function either directly or indirectly. This means that Frames from the video subsystem can be transferred using this class.

recvchannel

The stream to memory channel (if enabled in hardware)

Type:_SDMAChannel / _SGDMAChannel

sendchannel

The memory to stream channel (if enabled in hardware)

Type:_SDMAChannel / _SGDMAChannel

buffer_max_size

The maximum DMA transfer length.

Type:int

bindto = ['xilinx.com:ip:axi_dma:7.1']

set_up_rx_channel()

Set up the receive channel.

If receive channel is enabled, we will work out the max transfer size first. Then depending on (1) whether interrupt is enabled, and (2) whether SG mode is used, we will create the receive channel.

set_up_tx_channel()

Set up the transmit channel.

If transmit channel is enabled, we will work out the max transfer size first. Then depending on (1) whether interrupt is enabled, and (2) whether SG mode is used, we will create the transmit channel.