pynq.pl_server.embedded_device Module

The pynq.pl_server.embedded_device module extends the device class to work with Xilinx Run Time (XRT) embedded devices.

class pynq.pl_server.embedded_device.BinfileHandler(filepath)

Bases: pynq.pl_server.embedded_device.BitstreamHandler

get_bin_data()

Get the binary data of the bitstream in a form suitable for passing to FPGA manager

class pynq.pl_server.embedded_device.BitfileHandler(filepath)

Bases: pynq.pl_server.embedded_device.BitstreamHandler

get_bin_data()

Get the binary data of the bitstream in a form suitable for passing to FPGA manager

class pynq.pl_server.embedded_device.BitstreamHandler(filepath)

Bases: object

Base class for handling various formats of bitstreams

For a bitstream at least one of get_xclbin_data and get_hwh_data should return valid data in order for the bitstream to be used the Overlay class. If the bitstream is going to be used with the Bitstream class then only get_bin_data is required.

get_bin_data()

Get the binary data of the bitstream in a form suitable for passing to FPGA manager

get_dtbo_data()

Return the device tree overlay for the bitstream

Should be None if no device tree overlay is present

get_hwh_data()

Return the hardware handoff file for the bitstream

Should be None if no HWH data is available

get_parser(partial: bool = False)

Returns a parser object for the bitstream

The returned object contains all of the data that was processed from both the HWH and Xclbin metadata attached to the object. Note that the parser may contain synthetic xclbin data where that is necessary

get_xclbin_data()

Return the xclbin data for the bitstream

Should be None if no data exists

is_xsa()

Returns true if this is an XSA file, false otherwise

exception pynq.pl_server.embedded_device.CacheMetadataError

Bases: Exception

An exception that is raised when there is no cached metadata

class pynq.pl_server.embedded_device.EmbeddedDevice

Bases: pynq.pl_server.xrt_device.XrtDevice

Device for interacting with Zynq-7000 and Zynq US+ logic

For Zynq and Zynq US+ a hybrid approach is taken whereby FPGA manager is used to program the device, /dev/mem is used to interact with IP in the programmable logic and XRT is used to allocate memory.

The device can take multiple forms of bitstream and metadata files:

• .bit/.bin file with HWH metadata
• .bit/.bin file with XclBin metadata
• .bit/.bin file with both HWH and Xclbin metadata
• Xclbin file containing a bitstream
• XSA file containing a bitstream

In situations where an xclbin file isn’t provided a temporary one will be created so that all memories in the design can be allocated with XRT.

Note that a bitstream will need to be loaded before any allocation can occur.

BS_FPGA_MAN = '/sys/class/fpga_manager/fpga0/firmware'

BS_FPGA_MAN_FLAGS = '/sys/class/fpga_manager/fpga0/flags'

default_memory

download(bitstream, parser=None)

gen_cache(bitstream, parser=None)

Generates the cache of the metadata even if no download occurred

get_bitfile_metadata(bitfile_name: str, partial: bool = False)

get_memory(description)

mmap(base_addr, length)

set_axi_port_width(parser)

This method will set the AXI port width.

This is useful to resolve discrepancy between the PS configurations during boot and the PS configurations required by the bitstream. It is usually to be resolved for full bitstream reconfiguration.

Check https://www.xilinx.com/support/answers/66295.html for more information on the meaning of register values.

Currently only zynq ultrascale devices support data width changes.

class pynq.pl_server.embedded_device.EmbeddedXrtMemory(device, desc)

Bases: pynq.pl_server.xrt_device.XrtMemory

mmio

read(address)

write(address, value)

class pynq.pl_server.embedded_device.XclbinHandler(filepath)

Bases: pynq.pl_server.embedded_device.BitstreamHandler

get_bin_data()

Get the binary data of the bitstream in a form suitable for passing to FPGA manager

get_xclbin_data()

Return the xclbin data for the bitstream

Should be None if no data exists

class pynq.pl_server.embedded_device.XsafileHandler(filepath)

Bases: pynq.pl_server.embedded_device.BitstreamHandler

get_bin_data()

Get the binary data of the bitstream in a form suitable for passing to FPGA manager

pynq.pl_server.embedded_device.bit2bin(bit_data)

Convert an in-memory .bit file to .bin data for fpga_manager

pynq.pl_server.embedded_device.parse_bit_header(bit_data)

The method to parse the header of a bitstream.

The returned dictionary has the following keys: “design”: str, the Vivado project name that generated the bitstream; “version”: str, the Vivado tool version that generated the bitstream; “part”: str, the Xilinx part name that the bitstream targets; “date”: str, the date the bitstream was compiled on; “time”: str, the time the bitstream finished compilation; “length”: int, total length of the bitstream (in bytes); “data”: binary, binary data in .bit file format

Returns:A dictionary containing the header information. Return type:Dict

Note

Implemented based on: https://blog.aeste.my/?p=2892