pynq.ps Module¶
The pynq.ps module facilitates management of the Processing System (PS) and PS/PL interface. It provides Register and Clocks classes for setting and getting of ARM Architecture register bits. The Register class is used in the Clocks class for getting the ARM clock frequency, and getting and setting the frequencies Programmable Logic (PL) clocks.
-
class
pynq.ps.
Clocks
[source]¶ Bases:
object
Class for all the PS and PL clocks exposed to users.
With this class, users can get the CPU clock and all the PL clocks. Users can also set PL clocks to other values using this class.
-
cpu_mhz
¶ float – The clock rate of the CPU, measured in MHz.
-
fclk0_mhz
¶ float – The clock rate of the PL clock 0, measured in MHz.
-
fclk1_mhz
¶ float – The clock rate of the PL clock 1, measured in MHz.
-
fclk2_mhz
¶ float – The clock rate of the PL clock 2, measured in MHz.
-
fclk3_mhz
¶ float – The clock rate of the PL clock 3, measured in MHz.
-
-
class
pynq.ps.
ClocksMeta
[source]¶ Bases:
type
Meta class for all the PS and PL clocks not exposed to users.
Since this is the meta class for all the clocks, no attributes or methods are exposed to users. Users should use the class Clocks instead.
Note
If this class is parsed on an unsupported architecture it will issue a warning and leave class variables undefined
-
cpu_mhz
¶ The getter method for CPU clock.
The returned clock rate is measured in MHz.
-
fclk0_mhz
¶ The getter method for PL clock 0.
This method will read the register values, do the calculation, and return the current clock rate.
Returns: The returned clock rate measured in MHz. Return type: float
-
fclk1_mhz
¶ The getter method for PL clock 1.
This method will read the register values, do the calculation, and return the current clock rate.
Returns: The returned clock rate measured in MHz. Return type: float
-
fclk2_mhz
¶ The getter method for PL clock 2.
This method will read the register values, do the calculation, and return the current clock rate.
Returns: The returned clock rate measured in MHz. Return type: float
-
fclk3_mhz
¶ The getter method for PL clock 3.
This method will read the register values, do the calculation, and return the current clock rate.
Returns: The returned clock rate measured in MHz. Return type: float
-
set_fclk
(clk_idx, div0=None, div1=None, clk_mhz=100.0)[source]¶ This method can set a PL clock frequency.
Users have to specify the index of the PL clock to be changed. For example, for fclk1, clk_idx is 1.
The CPU clock, by default, should not get changed.
Users have 2 options: 1. specify the 2 frequency divider values directly, or 2. specify the clock rate, in which case the divider values will be calculated.
Note
In case div0 and div1 are both specified, the parameter clk_mhz will be ignored.
Parameters: - clk_idx (int) – The index of the PL clock to be changed, from 0 to 3.
- div0 (int) – The first frequency divider value.
- div1 (int) – The second frequency divider value.
- clk_mhz (float) – The clock rate in MHz.
-
-
class
pynq.ps.
Register
(address, width=32)[source]¶ Bases:
object
Register class that allows users to access registers easily.
This class supports register slicing, which makes the access to register values much more easily. Users can either use +1 or -1 as the step when slicing the register. By default, the slice starts from MSB to LSB, which is consistent with the common hardware design practice.
For example, the following slices are acceptable: reg[31:13] (commonly used), reg[:], reg[3::], reg[:20:], reg[1:3], etc.
Note
The slicing endpoints are closed, meaning both of the 2 endpoints will be included in the final returned value. For example, reg[31:0] will return a 32-bit value; this is consistent with most of the hardware definitions.
-
address
¶ int – The address of the register.
-
width
¶ int – The width of the register, e.g., 32 (default) or 64.
-