# Copyright (c) 2019, Xilinx, Inc.
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__author__ = "Peter Ogden"
__copyright__ = "Copyright 2019, Xilinx"
__email__ = "pynq_support@xilinx.com"
import atexit
import os
import struct
import warnings
import numpy as np
from .server import DeviceClient, DeviceServer
[docs]class Device(metaclass=DeviceMeta):
"""Construct a new Device Instance
This should be called by subclasses providing a globally unique
identifier for the device.
Parameters
----------
tag: str
The unique identifier associated with the device
server_type: str
Indicates the type of PL server to use. Its value can only be one
of the following ["global"|"local"|"fallback"], where "global" will
use a global PL server, "local" will spawn a local PL server (i.e.
only associated to the current Python process), and "fallback" will
attempt to use a global PL server and fallback to local in case it
fails, warning the user. Default is "fallback".
warn: bool
Warn the user when falling back to local PL server.
Default is False
"""
start_global = False
"""
Class attribute that can override 'server_type' if set to True
when 'global' or 'fallback' are used
"""
def __init__(self, tag, server_type="fallback", warn=False):
# Args validation
if type(tag) is not str:
raise ValueError("Argument 'tag' must be a string")
if server_type not in ["global", "local", "fallback"]:
raise ValueError("Argument 'server_type' can only be set to "
"'global', 'local' or 'fallback'")
if server_type in ["global", "fallback"]:
self._server = None
if not DeviceClient.accessible(tag):
if self.start_global:
# global PL server will be started later
server_type = None
elif server_type == "global":
raise ConnectionError("Could not connect to global PL "
"server")
elif warn:
warnings.warn("Could not connect to global PL server, "
"falling back to local PL server", Warning)
else:
server_type = None # avoid fallback to local when successful
if server_type in ["local", "fallback"]:
tag = "{}.{}".format(tag, os.getpid())
if not DeviceClient.accessible(tag):
self._server = DeviceServer(tag)
self._server.start()
self.tag = tag
self._client = DeviceClient(tag)
atexit.register(self.close)
[docs] def close(self):
if self._server:
self._server.stop()
self._server = None
@property
def ip_dict(self):
"""The getter for the attribute `ip_dict`.
Returns
-------
dict
The dictionary storing addressable IP instances; can be empty.
"""
return self._client.ip_dict
@property
def gpio_dict(self):
"""The getter for the attribute `gpio_dict`.
Returns
-------
dict
The dictionary storing the PS GPIO pins.
"""
return self._client.gpio_dict
@property
def interrupt_pins(self):
"""The getter for the attribute `interrupt_pins`.
Returns
-------
dict
The dictionary storing the interrupt endpoint information.
"""
return self._client.interrupt_pins
@property
def interrupt_controllers(self):
"""The getter for the attribute `interrupt_controllers`.
Returns
-------
dict
The dictionary storing interrupt controller information.
"""
return self._client.interrupt_controllers
@property
def bitfile_name(self):
"""The getter for the attribute `bitfile_name`.
Returns
-------
str
The absolute path of the bitstream currently on PL.
"""
return self._client.bitfile_name
@property
def hierarchy_dict(self):
"""The getter for the attribute `hierarchy_dict`
Returns
-------
dict
The dictionary containing the hierarchies in the design
"""
return self._client.hierarchy_dict
@property
def timestamp(self):
"""The getter for the attribute `timestamp`.
Returns
-------
str
Bitstream download timestamp.
"""
return self._client.timestamp
@property
def devicetree_dict(self):
"""The getter for the attribute `devicetree_dict`
Returns
-------
dict
The dictionary containing the device tree blobs.
"""
return self._client.devicetree_dict
@property
def mem_dict(self):
"""The getter for the attribute `mem_dict`
Returns
-------
dict
The dictionary containing the memory spaces in the design
"""
return self._client.mem_dict
[docs] def allocate(self, shape, dtype, **kwargs):
"""Allocate an array on the device
Returns a buffer on memory accessible to the device
Parameters
----------
shape : tuple(int)
The shape of the array
dtype : np.dtype
The type of the elements of the array
Returns
------
PynqBuffer
The buffer shared between the host and the device
"""
return self.default_memory.allocate(shape, dtype, **kwargs)
[docs] def reset(self, parser=None, timestamp=None, bitfile_name=None):
"""Reset all the dictionaries.
This method must be called after a bitstream download.
1. In case there is a `hwh` file, this method will reset
the states of the IP, GPIO, and interrupt dictionaries .
2. In case there is no `hwh` file, this method will simply
clear the state information stored for all dictionaries.
An existing parser given as the input can significantly reduce
the reset time, since the PL can reset based on the
information provided by the parser.
Parameters
----------
parser : HWH
A parser object to speed up the reset process.
timestamp : str
The timestamp to embed in the reset
bitfile_name : str
The bitfile being loaded as part of the reset
"""
self._client.reset(parser, timestamp, bitfile_name)
[docs] def clear_dict(self):
"""Clear all the dictionaries stored in PL.
This method will clear all the related dictionaries, including IP
dictionary, GPIO dictionary, etc.
"""
self._client.clear_dict()
[docs] def load_ip_data(self, ip_name, data, zero=False):
"""This method writes data to the addressable IP.
Note
----
The data is assumed to be in binary format (.bin). The data
name will be stored as a state information in the IP dictionary.
Parameters
----------
ip_name : str
The name of the addressable IP.
data : str
The absolute path of the data to be loaded.
zero : bool
Zero out the address of the IP not covered by data
Returns
-------
None
"""
from pynq import MMIO
self._client.load_ip_data(ip_name, data)
ip_dict = self.ip_dict
with open(data, 'rb') as bin_file:
size = os.fstat(bin_file.fileno()).st_size
target_size = ip_dict[ip_name]['addr_range']
if size > target_size:
raise RuntimeError("Binary file too big for IP")
mmio = MMIO(ip_dict[ip_name]['phys_addr'], target_size,
device=self)
buf = bin_file.read(size)
if len(buf) % 4 != 0:
padding = 4 - len(buf) % 4
buf += b"\x00" * padding
size += padding
mmio.write(0, buf)
if zero and size < target_size:
mmio.write(size, b'\x00' * (target_size - size))
[docs] def update_partial_region(self, hier, parser):
"""Merge the parser information from partial region.
Combine the currently PL information and the partial HWH file
parsing results.
Parameters
----------
hier : str
The name of the hierarchical block as the partial region.
parser : HWH
A parser object for the partial region.
"""
self._client.update_partial_region(hier, parser)
[docs] def clear_devicetree(self):
"""Clear the device tree dictionary.
This should be used when downloading the full bitstream, where all the
dtbo are cleared from the system.
"""
self._client.clear_devicetree()
[docs] def insert_device_tree(self, abs_dtbo):
"""Insert device tree segment.
For device tree segments associated with full / partial bitstreams,
users can provide the relative or absolute paths of the dtbo files.
Parameters
----------
abs_dtbo : str
The absolute path to the device tree segment.
"""
self._client.insert_device_tree(abs_dtbo)
[docs] def remove_device_tree(self, abs_dtbo):
"""Remove device tree segment for the overlay.
Parameters
----------
abs_dtbo : str
The absolute path to the device tree segment.
"""
self._client.remove_device_tree(abs_dtbo)
[docs] def shutdown(self):
"""Shutdown the AXI connections to the PL in preparation for
reconfiguration
"""
from pynq import MMIO
ip = self.ip_dict
for name, details in ip.items():
if details['type'] == 'xilinx.com:ip:pr_axi_shutdown_manager:1.0':
mmio = MMIO(details['phys_addr'], device=self)
# Request shutdown
mmio.write(0x0, 0x1)
i = 0
while mmio.read(0x0) != 0x0F and i < 16000:
i += 1
if i >= 16000:
warnings.warn("Timeout for shutdown manager. It's likely "
"the configured bitstream and metadata "
"don't match.")
[docs] def post_download(self, bitstream, parser):
if not bitstream.partial:
import datetime
t = datetime.datetime.now()
bitstream.timestamp = "{}/{}/{} {}:{}:{} +{}".format(
t.year, t.month, t.day,
t.hour, t.minute, t.second, t.microsecond)
self.reset(parser, bitstream.timestamp, bitstream.bitfile_name)
[docs] def has_capability(self, cap):
"""Test if the device as a desired capability
Parameters
----------
cap : str
The desired capability
Returns
-------
bool
True if the devices support cap
"""
if not hasattr(self, 'capabilities'):
return False
return cap in self.capabilities and self.capabilities[cap]
def _preload_binfile(bitstream):
bitstream.binfile_name = os.path.basename(
bitstream.bitfile_name) + '.bin'
bitstream.firmware_path = os.path.join('/lib/firmware',
bitstream.binfile_name)
bit_dict = parse_bit_header(bitstream.bitfile_name)
if bit_dict != bitstream.bit_data:
bitstream.bit_data = bit_dict
bit_buffer = np.frombuffer(bit_dict['data'], 'i4')
bin_buffer = bit_buffer.byteswap()
bin_buffer.tofile(bitstream.firmware_path, "")
ZU_FPD_SLCR_REG = {
'C_MAXIGP0_DATA_WIDTH': {
'FPD_SLCR.AXI_FS.DW_SS0_SEL': {
'addr': 0xFD615000,
'field': [9, 8]
}
},
'C_MAXIGP1_DATA_WIDTH': {
'FPD_SLCR.AXI_FS.DW_SS1_SEL': {
'addr': 0xFD615000,
'field': [11, 10]
}
},
'C_MAXIGP2_DATA_WIDTH': {
'LPD_SLCR.AXI_FS.DW_SS2_SEL': {
'addr': 0xFF419000,
'field': [9, 8]
}
}
}
ZU_FPD_SLCR_VALUE = {
'32': 0,
'64': 1,
'128': 2
}
ZU_AXIFM_REG = {
'C_SAXIGP0_DATA_WIDTH': {
'AFIFM0.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD360000,
'field': [1, 0]
},
'AFIFM0.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD360014,
'field': [1, 0]
}
},
'C_SAXIGP1_DATA_WIDTH': {
'AFIFM1.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD370000,
'field': [1, 0]
},
'AFIFM1.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD370014,
'field': [1, 0]
}
},
'C_SAXIGP2_DATA_WIDTH': {
'AFIFM2.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD380000,
'field': [1, 0]
},
'AFIFM2.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD380014,
'field': [1, 0]
}
},
'C_SAXIGP3_DATA_WIDTH': {
'AFIFM3.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD390000,
'field': [1, 0]
},
'AFIFM3.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD390014,
'field': [1, 0]
}
},
'C_SAXIGP4_DATA_WIDTH': {
'AFIFM4.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD3A0000,
'field': [1, 0]
},
'AFIFM4.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD3A0014,
'field': [1, 0]
}
},
'C_SAXIGP5_DATA_WIDTH': {
'AFIFM5.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFD3B0000,
'field': [1, 0]
},
'AFIFM5.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFD3B0014,
'field': [1, 0]
}
},
'C_SAXIGP6_DATA_WIDTH': {
'AFIFM6.AFIFM_RDCTRL.FABRIC_WIDTH': {
'addr': 0xFF9B0000,
'field': [1, 0]
},
'AFIFM6.AFIFM_WRCTRL.FABRIC_WIDTH': {
'addr': 0xFF9B0014,
'field': [1, 0]
}
}
}
ZU_AXIFM_VALUE = {
'32': 2,
'64': 1,
'128': 0
}
[docs]class XlnkDevice(Device):
"""Device sub-class for Xlnk based devices
"""
BS_FPGA_MAN = "/sys/class/fpga_manager/fpga0/firmware"
BS_FPGA_MAN_FLAGS = "/sys/class/fpga_manager/fpga0/flags"
@classmethod
def _probe_(cls):
if os.path.exists('/dev/xlnk'):
return [XlnkDevice()]
else:
return []
_probe_priority_ = 100
def __init__(self):
super().__init__("xlnk")
from pynq import Xlnk
self.default_memory = Xlnk()
self.capabilities = {
'MEMORY_MAPPED': True
}
@property
def name(self):
if "BOARD" in os.environ:
return os.environ["BOARD"]
else:
raise RuntimeError("Could not retrieve ZYNQ device name. BOARD "
"env not set")
[docs] def get_memory(self, description):
if description['type'] == 'PSDDR':
return self.default_memory
raise RuntimeError('Only PS memory supported for ZYNQ devices')
[docs] def mmap(self, base_addr, length):
import mmap
euid = os.geteuid()
if euid != 0:
raise EnvironmentError('Root permissions required.')
# Align the base address with the pages
virt_base = base_addr & ~(mmap.PAGESIZE - 1)
# Calculate base address offset w.r.t the base address
virt_offset = base_addr - virt_base
# Open file and mmap
mmap_file = os.open('/dev/mem', os.O_RDWR | os.O_SYNC)
mem = mmap.mmap(mmap_file, length + virt_offset,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=virt_base)
os.close(mmap_file)
array = np.frombuffer(mem, np.uint32, length >> 2, virt_offset)
return array
[docs] def set_axi_port_width(self, parser):
"""This method will set the AXI port width.
This is useful to resolve discrepancy between the PS configurations
during boot and the PS configurations required by the bitstream. It
is usually to be resolved for full bitstream reconfiguration.
Check https://www.xilinx.com/support/answers/66295.html for more
information on the meaning of register values.
Currently only zynq ultrascale devices support data width changes.
"""
from pynq.registers import Register
parameter_dict = parser.ip_dict[parser.ps_name]['parameters']
if parser.family_ps == 'zynq_ultra_ps_e':
for para in ZU_FPD_SLCR_REG:
if para in parameter_dict:
width = parameter_dict[para]
for reg_name in ZU_FPD_SLCR_REG[para]:
addr = ZU_FPD_SLCR_REG[para][reg_name]['addr']
f = ZU_FPD_SLCR_REG[para][reg_name]['field']
Register(addr)[f[0]:f[1]] = ZU_FPD_SLCR_VALUE[width]
for para in ZU_AXIFM_REG:
if para in parameter_dict:
width = parameter_dict[para]
for reg_name in ZU_AXIFM_REG[para]:
addr = ZU_AXIFM_REG[para][reg_name]['addr']
f = ZU_AXIFM_REG[para][reg_name]['field']
Register(addr)[f[0]:f[1]] = ZU_AXIFM_VALUE[width]
[docs] def download(self, bitstream, parser=None):
if not bitstream.binfile_name:
_preload_binfile(bitstream)
if not bitstream.partial:
self.shutdown()
flag = '0'
else:
flag = '1'
with open(self.BS_FPGA_MAN_FLAGS, 'w') as fd:
fd.write(flag)
with open(self.BS_FPGA_MAN, 'w') as fd:
fd.write(bitstream.binfile_name)
if parser is not None:
self.set_axi_port_width(parser)
super().post_download(bitstream, parser)